1. Field of the Invention
The present invention relates to a driving method of a nonvolatile memory and a nonvolatile memory used in the same method. More specifically, the present invention relates to a read and write system for storage of one bit of a two bit MONOS-typed memory cell and a nonvolatile memory employing the read and write system.
2. Description of the Related Art
Recently, as one kind of nonvolatile memory such as a flash memory or an EEPROM, which employs a floating gate system using a conductive material, such as polysilicon, as a material for storage of bit information, a MONOS-typed memory using an ONO film, as a composite film including silicon oxide (SiO) films and a nitrogen oxide (SiN) film, as an insulator, interposed therebetween, is being widely used to obtain better integration and reliability.
Such a MONO-typed memory has a virtual ground array configured with diffusion bit lines and word lines so as to obtain high integration, as shown in FIG. 14A. FIG. 14B shows a sectional view of a memory cell, taken along the line A-B in FIG. 14A. As shown in FIG. 14B, a transistor cell (typically, an Nch transistor) includes diffusion bit lines 34 below a LOCOS oxide film 33 as a drain D and a source S, respectively, and a word line 32 as a gate electrode, with an ONO film as a gate insulating film interposed between the bit lines 34 and the word line 32.
A program operation uses injection of hot electrons by a channel current flow between the drain and the source. The injected hot electrons are locally captured by a silicon nitride film of the ONO film at the vicinity of junction edges 36 of the diffusion bit lines 34, that is, in the vicinity of a junction at a drain electrode side at the time of programming.
Now, a read operation of the above-constructed memory cell will be described with reference to FIGS. 15A and 15B.
FIG. 15A shows an aspect of a conductive channel in an erase state of the memory cell. A cell current is read by applying a bias voltage to a saturated region. Since there exist no the injected hot electrons, an equivalent current flows for interchange between the drain D and the source S. The conductive channel at the drain electrode side is pinched off by an electric field of the drain D.
FIG. 15B shows an aspect of the conductive channel in a program state (a condition where charges are set in BIT1) of the memory cell. The memory cell is biased to the saturated region and hot electrons injected in the drain D are read by interchanging between the drain and the source for program.
Hot electrons injected in the source S suppress increase of a threshold value of the source S, that is, formation of the conductive channel, and lower the cell current, as compared to the erase state (no injected charge).
The hot electrons injected in the drain D have little effect on the cell current. This is because the saturated region must be deep as a read bias condition, the conductive channel in the vicinity of injected electrons at the drain D is not present by being pinched off, and the electrons flow as a punch-through between an edge of the conductive channel and the drain D.
Using such a characteristic, at least one bit is stored in each of the drain D and the source S, that is, the total of 2 bits can be stored in one memory cell.
An erase operation is performed by taking a gate voltage as a zero or negative voltage, applying a positive potential to one of a source junction and a drain junction, and using hole carriers initiated by a band-to-band tunneling effect at depletion region due to heavily doped (1E18 or so) impurity regions of the diffusion bit lines.
The hole carriers produced by the band-to-band tunneling effect are sufficiently accelerated by a lateral electric field applied between bit line junctions and a substrate and are injected as hot holes in the vicinity of the injected electrons of the ONO film, thus neutralizing the injected electrons.
If an electric field is simultaneously applied to the drain D and the source S, since the horizontal electric field important in generation of the hot holes is weakened, thus lowering efficiency of the erase operation, it is typically preferable to perform the erase operation for each diffusion bit line.
From the point of view of reliability, the MONOS-typed memory implements a high retention characteristic by local capture of electrons. In a memory cell employing the floating gate system having no local capture mechanism, injected electrons uniformly spread on a conductive floating gate surface. It is necessary to maintain an insulating property of the entire floating gate in order to maintain retentive property of electrons, and a leak at a local defect leads to fatal deterioration of the retention characteristic.
On the other hand, in the MONOS-typed memory, since the ONO film itself is a good insulator, there is no fatal detect even if a portion of the ONO film have any defect, as long as the portion is not a charge storage portion, thus allowing a very high tolerance to the defect.
The above-mentioned conventional two bit MONOS-typed memory is disclosed in (Device) JP-W-2001-512290, (Device) U.S. Pat. No. 5,768,192, (Device) U.S. Pat. No. 6,011,725, etc. In addition, a two bit MONOS-typed memory cell may have a virtual ground array structure with highly reduced area (5F2 or so) of a memory array by sharing the bit lines with adjacent tow bit MONOS-typed memory cells and making two bit MONOS-typed memory cells not to contact each other, as described earlier.
The virtual ground array has a very simple structure where the word lines 32 are perpendicular to the diffusion bit lines 34 embedded below the LOCOS oxide films 33, with the ONO film 31 as the gate insulating film, as shown in FIG. 14A. Such a basic architecture of the virtual ground array is disclosed in (Virtual ground array) U.S. Pat. No. 5,204,835 and (Virtual ground array) U.S. Pat. No. 5,151,375, and an architecture specialized by two bit read of the MONOS-typed memory cells is disclosed in (MONOS-typed virtual ground array) U.S. Pat. No. 5,963,465.
As one example of methods of reading memory data from the virtual ground array, there is a source side read method. In the source side read method, a reading operation is performed in a series of orders of discharge of the diffusion bit lines to ground, making impedance of the diffusion bit lines high, selection of accessing diffused bit lines, application of a read bias voltage (2 V or so) to drain side bit lines, connection of source lines to sense amplifiers, selection of a word line, etc. Details of the data reading method are disclosed in (Source side reading method) U.S. Pat. No. 6,134,165.
Now, problems of the above-described two bit MONOS-typed memory cell to be solved by the present invention will be described below. The two bit MONOS-typed memory cell is difficult to obtain a high threshold voltage Vth since a program state is realized only by charges locally injected into a local source electrode side, and requires a relatively high drain bias for two bit separation.
Accordingly, since a cell current ratio of the program state to the erase state is small at the end of life, for example, 1:2, and a large difference (margin) between a cell current and a reference cell current or between a cell voltage and a reference voltage can not be taken, it is difficult to perform a high speed reading operation with high reliability.
The reading operation with high reliability as used herein means that the difference between the cell current and the reference cell current or between the cell voltage and the reference voltage is sufficiently large, even though the cell current is varied due to possible deterioration of memory cells, and sense amplifiers can correctly read logical bit values stored in memory cells. In addition, for a two bit separation reading operation, there is a need to pinch off a conductive channel at an area near a drain of a memory cell with a drain voltage of the memory cell being at least more than a saturated voltage. The drain voltage of the memory cell is typically higher than that of a floating gate-typed memory cell. Moreover, there may occur a disturbance of storage data due to a soft program effect of the reading (an effect that data are weakly written into erased cells due to not electron injection at a low electric field in the reading operation).
In addition, the two bit MONOS-typed memory cell has greater power consumption than that of the floating gate-typed memory cell. More specifically, the two bit MONOS-typed memory cell has a problem in that it has great power consumption due to a high drain bias voltage for a cell of an erase state and due to a high leak current and a high drain bias voltage for a cell of a program state.
Next, problems of the above-described virtual ground array to be solved by the present invention will be described below. For the virtual ground array, the reading operation of the cell current is performed by first discharging the entire bit lines (drains and sources) to a ground potential before a memory cell is selected, and then putting the discharged entire bit lines into a high impedance state. A cell current of a desired cell is read by applying a gate bias voltage to a word line, applying a drain voltage (1˜2 V) at the Lime of reading to a drain, and connecting source potential side bit lines to sense amplifiers.
The diffused bit lines at the source side are shared with adjacent cells. Accordingly, the cell current is leaked into the adjacent cells depending on a program state, i.e., impedance, of the adjacent cells in a word line direction of the source side. When the adjacent cells are in an erase state, the cell current is leaked into the adjacent cells, and the sense amplifiers determine that a cell current input thereto is smaller than that of an actual cell current.
Such a phenomenon causes erroneous determination (determining that writing of data into a cell further requiring a program pulse is completed) of a verification operation (measuring a cell current or a threshold value after application of a program pulse, and verifying whether or not further pulses are required) in a cell program operation.
The amount of leak of the cell current into the adjacent cells is affected by the program state of a cell group connected to the word lines of the source side. On this account, distribution of current of programmed cells, being affected by a cell current depending on deviation of physical write characteristics of a memory, a memory array structure and written data, becomes wide.
Accordingly, since the charge state distribution of the memory cell is wide, a margin of conditions must be considered to guarantee the reliability, and a margin required as a bias condition for reading becomes large, which results in insufficient use of characteristics of the memory cell.
To avoid this, typically, time for writing must be increased, such as reading in advance information of adjacent bits of cells to be programmed, applying further pulses when adjacent bits of the source side are in the erase state, and adjusting a determination level of program verification, thus requiring sacrifice of performance of the memory cells to some degree. An effect that a cell current to be read is varied depending on the program state of the adjacent cells is a problem to be solved for a reading margin and reliability of the virtual ground array.